USBHS-PHY - USB 2.0 High Speed PHY for 28-180nm Processes

The USBHS-PHY is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 Physical Layer for Host and Device applications. The USBHS-PHY consists of the following blocks:

• High-Speed, Full Speed and Low Speed analog drivers and receivers
• Squelch and disconnect detectors
• Clock and Data Recovery (CDR/PLL) with low-jitter 480MHz PLL
• XTAL oscillator with an option to use external clock
• Integrated pull-up/pull-down resistors
• Self calibrated termination resistors
• VBUS sense circuits
• Digital Control Logic