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USBHSIC-PHY - USB High Speed Inter Chip PHY for 28-180nm Processes

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The USBHSIC-PHY is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 High Speed Inter Chip (HSIC) layer for USB 2.0 High Speed Device and Host applications.

The USBHSIC-PHY consists of a logic macro, which is available as either hard or soft IP, and a hard-IP block that contains the special driver  circuit that is mandated by the HSIC specification.

The HSIC standard exists because there are many applications where it makes sense to embed a subsystem that uses USB 2.0 within embedded applications that do not need to be connected to external devices.

The USBHSIC-PHY can be used for subsystems within a smartphone. The big advantage over conventional USB2 is the elimination of most of the power consumption and most of the chip area that would be required for conventional USB2 PHYs.

  • Highlights
  • Target Technology
  • Applications
  • Deliverables
  • 8-bit (optionally 16-bit) parallel UTMI+ interface
  • Built-in Self Test
  • Scan-based DFT
  • 1.2±10% driver supply
The USBHSIC-PHY is portable to any technology node from 28 to 180nm. Please contact us to find our more about availability of a specific technology node.

The USBHSIC-PHY can be used for a variety of applications implementing internal chip-to-chip communication, like set top boxes, mass storage devices and mobile applications.

Deliverables

  • Design files kit
  • Documentation
  • 30 days of technical support 
  • 90 days of warranty against defects

Delivery Options

  • 8-bit (optionally 16-bit) parallel UTMI+interface
  • Built-in Self Test
  • Scan-based DFT
  • 1.2±10% driver supply

Downloads

Related Products

USBHS-OTG-MPD - USB 2.0 High Speed Device and Embedded Host Controller that meets the 2.0 revision of the USB specification.

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