Highlights

• Meets Atmel^® SPI interface specification
• Full duplex mode
• Three-wire synchronous transfers except for a four–wire transfer when more than one slave is present
• Four transfer protocols available with programmable clock polarity and clock phase

Benefits

• Slave Clock rate of up to Fclk/4
• Easy switching between Master and Slave modes
• Standard in a broad range of applications
• Seven programmable SPI Master baud rates from Fclk/128 up to Fclk/2 clock rates

• SFR interface width
• Software or hardware configuration of register flags

• Converters (ADC and DAC)
• Memories (EEPROM and FLASH)
• Real Time Clocks (RTC)

• Sensors (temperature, pressure)
• Microcontrollers networking
• RF transceivers (Bluetooth, ZigBee, ISMband)

Deliverables

• VDHL/Verilog source code
• Synthesis support for Synopsys® tools with a set of synthesis scripts
• Simulation support for Mentor Graphics®, Aldec® and Cadence® tools with a set of scripts and macros
  
• Extensive VHDL/Verilog 2001 test bench
• Documentation
• 30 days of technical support 
• 90 days of warranty against defects

Delivery Options

• EDIF netlist for FPGA and low volume production
• One-year maintenance
• On-site support and training