• HDLC protocol compatible
• PLB and generic system bus interfaces
• LAPB/LAPD controlling machine
• Bit stuffing, flag generation and support for modem lines
• Receive Length Check

• Auto, non-auto and transparent modes of receive operation
• 64-bytes long receive/transmit FIFOs
• Single or dual independent channel versions
• Interrupt or DMA transfer modes for receive transmit blocks

• Hardware support for LAPB/LAPD means only minor frame processing in the target microcontroller
• Built-in timer for retransmission
• Support for line speeds of up to 10Mbit/s

• Support for an external DMA controller speeds up data exchange between CPU and the HDLC controller
• Very easy channel adding
• Shared interrupt line for 11 internal interrupts means no need for complicated interrupt controllers in CPU

• X.25 link control
• Physical link maintenance and quality monitoring of wide area networks

• ISDN applications
• General purpose telecommunication applications

Deliverables

• VDHL/Verilog source code
• Synthesis support for Synopsys® tools with a set of synthesis scripts
• Simulation support for Mentor Graphics®, Aldec® and Cadence® tools with a set of scripts and macros
  
• Extensive test bench
• Documentation
• 30 days of technical support 
• 90 days of warranty against defects

Delivery Options

• EDIF netlist for FPGA and low volume production
• One-year maintenance
• On-site support and training