
Since the development of the first Evatronix IP core in 1997, we have gained extensive experience in designing pin-to-pin or functionally equivalent IP cores to the existing obsolete chips.
Our detailed analysis of the original chip’s behavior is performed with Evatronix proprietary hardware modeling tool. The next stages, FPGA prototyping and verification in original chip environment, further secure hardware and software compatibility of the replacement IP with the existing application.
All of Evatronix obsolete IP cores are provided with the same support and guarantee as other products.
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How to Achieve The Highest Data Rate in NAND Flash Application
The recent years brought significant changes and improvements to the NAND Flash technology, and this article will elaborate to how to take full advantage of the latest features of the controllers and standards while avoiding the traps of the technology.
Hardware solutions to the Challenges of multimedia IP functional verification
This paper discusses the functional verification of IP cores and problems which arise during their implemenation in today’s advanced applications.
Straightforward IP Integration with IP-XACT RTL-TLM Switching
This paper gives the results of experimentations done for the packaging of a USB OTG controller respecting the IP-XACT schema. It presents the advantages and the technical facts for an IP provider to deliver a standardized files package for documentation, integration and verification purposes.
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