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JPEG 2000-2K - JPEG 2000-compatible DCI 2K and Full HD Image Encoder

JPEG2000-2K-block-diagram

The JPEG 2000-2K is an entirely hardware implementation of the JPEG 2000 compression standard encoder based on the ISO/IEC 15444-1.

The codestream produced by JPEG 2000-2K  core is fully compliant  with the standard and its various features are supported.

The encoder performs multiple component transformation (reversible and irreversible), discrete wavelet transformation (with 9‑7 and 5‑3 filters), quantization, arithmetic entropy coding, rate control and JPEG 2000 stream formation. {article 575} {readmore:|.readon}{/article}

  • Highlights
  • Benefits
  • Applications
  • Deliverables
  • Compliant with ISO/IEC 15444-1 JPEG 2000 requirement
  • 3D compression support for 1080p 4:2:0 signal
  • Sub-frame latency
  • Target rate control
  • Flexible input image resolution with Full HD and Digital Cinema support
  • Configuration interface, video interface, codestream interface, external memory interface compliant with Open Core Protocol 2.2 (OCP)
  • HD, DCI 2K image resolutions support
  • Better image quality for lower bit-rates when compared to the JPEG standard, especially for HD and DCI 2K resolutions
  • Excellent performance to size ratio
  • Both lossless and lossy compression modes implemented
  • Customizable design: ASIC, Xilinx Virtex-5 and Virtex-6, Altera Stratix III and Stratix IV FPGAs
  • Digital still cameras and camcorders
  • Video mastering, archiving and acquisition
  • Post-production
  • Digital cinema systems
  • Video and imaging distribution systems
  • 3G mobile networks
  • Digital CCTV and security systems
  • Satellite imaging

Deliverables

  • VHDL source code
  • Synthesis support for Synopsys® and Cadence tools with a set of synthesis scripts 
  • Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros 
  • Extensive VHDL test bench
  • Documentation
  • 30 days of technical support 
  • 90 days of warranty against defects

Delivery Options

  • EDIF netlist for FPGA and low volume production
  • Verilog source code
  • One-year maintenance
  • On-site support and training

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