SLIMBUS-MGR - MIPI® SLIMbus Manager Controller

The SLIMBUS-MGR is a MIPI®-compliant SLIMbusSM Manager controller that implements Interface Device Class and Manager Device Class.

Thanks to an OCP interface and a rich set of wrappers, the IP core can be easily interfaced to every system bus standard, like AMBA® AHB, PLB, OPB, Wishbone and others.

It supports most advanced MIPI® SLIMbusSM features, which include dynamic bus reconfiguration and power consumption optimization.

The component was rigorously verified using complex functional testbench environment and simulators QuestaSim and NCSim. Moreover, state-of-the-art tools like Synopsys® Leda, TransEDA® CodeCoverage and Mentor Graphics® 0-In were used for the IP core’s validation.

  • Highlights
  • Benefits
  • Configurability
  • Applications
  • Deliverables
  • Compliant to MIPI® SLIMbus specification version 1.01.01
  • Full support for all core messages, bus reconfiguration and Request/ Clear Information commands
  • Automatic transmission of reply and report messages
  • Transmission of any messages prepared and written by the processor to the Transmit Buffer
  • Implementation of all mandatory and optional Core and Interface Information Elements 
  • Support for all mandatory and optional Core, Interface and Generic Information Elements
  • Implementation of isochronous and pushed data transmission protocols 
  • OCP processor interface with a set of wrappers to other bus interfaces (AMBA® AHB, PLB)
  • Extensive configurability options that can be set by either generic parameters or SFR settings
  • Placing audio data and control information on a single bus means no need for other control buses such as I2C or SPI
  • One bus for multiple simultaneous audio data streams at different sample rates and bit widths 
  • Dynamic bus reconfiguration for optimizing bus power consumption and allocating desired bandwidth for Control and Data channel
  • Can be adapted to any application
  • OCP data bus width
  • Depth of DPRAMs used by data ports
  • Number of data ports
  • Enumeration Addresses of Interface Size of Receive and Transmit Buffers
  • Size of queue for messages to be transmitted
  • Maximum number of automatic restransmissions
  • Disabling automatic reporting after change of Information Element bit (into active state)
  • Disabling automatic calculation of CRC
  • Almost-empty and almost-full levels for DMA operation
  • Instance value (part of EA)
  • SLIMbus interface for the system host control operation of the bus

Deliverables

  • RTL source code
  • Synthesis support for Synopsys® and Cadence® tools with a set of synthesis scripts 
  • Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros 
  • Extensive HDL test bench
  • Documentation
  • 30 days of technical support 
  • 90 days of warranty against defects

Delivery Options

  • EDIF netlist for FPGA and low volume production
  • IP-XACT 1.2/1.4 packaging
  • Evaluation system for Xilinx®/Altera® development board
  • Reference design for proprietary development board 
  • One-year maintenance
  • On-site support and training

Downloads

Similar Products

SLIMBUS-MGR-DPORT – extends the Manager Controller with DMA interface and ability to transfer and process multiple simultaneous data streams independently.

Related Products

SLIMBUS-FRM – implements Interface and Framer Device Classes with a programmable set of supported clock frequencies. The component fully supports advanced MIPI SLIMbusfeatures, like dynamic bus reconfiguration and framer handover. Furthermore, it implements all Core, Interface and Framer Information Elements and supports automatic transmission of reply and report messages.

SLIMBUS-DEV – implements Interface Device Class and Generic Device Class with up to 64 programmable data ports. Full compliance with the MIPI SLIMbus specification enables user to enjoy all benefits of the SLIMbus standard, which include dynamic bus reconfiguration, multiple simultaneous independent data transmissions and power consumption optimization.

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