SPDIF - Sony/Philips Digital Interface Controller

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The SPDIF controller implements the IEC 60958 interface (commonly known as Sony/Philips Digital Interface), a unidirectional and self- clocking interface for connecting digital audio equipment using the linear PCM coded audio samples.

All data collected by the SPDIF controller are stored in the internal core’s FIFO memory. The use of internal FIFO allows the system to process  relatively slow audio stream in the interrupt triggered subroutines.

The SPDIF can be also easily used for fast serial non-audio transmission. The SPDIF controller core can be easily integrated with the master system based on standard AMBA APB or AMBA AHB bus interface for further data processing.

  • Highlights
  • Benefits
  • Applications
  • Deliverables
  • Meets the SPDIF specification
  • AMBA AHB/APB, OPB, PLB and Avalon system bus interfaces available
  • Receiver/Transmitter modes are supported
  • Support for sample rates from 3kHz to 192 kHz (with 98MHz SPDIF system clock), 20/24 bit per sample
  • DMA Master handshake interfacing
  • Integrated AMBA APB or AMBA AHB slave wrapper to interface with the host AHB or APB controller
  • Configurable size of external FIFO (default value is 64 words)
  • Advanced configurability
  • Full resistance to input signal jitter defined by the IEC 60958
  • Compact, high performance architecture
  • Configurable internal FIFO for data streaming
  • Digital audio, video (DVD) and multimedia systems in general
  • High quality multi channel audio transmission – non PCM data
  • Fast serial non-audio transmission
  • Applications where optical serial communication is required (high immunity for EMC, low vulnerability for electrostatic discharge, secure systems with reduced EMC radiation)

Deliverables

  • VHDL/Verilog source code
  • Synthesis support for Synopsys and Cadence tools with a set of synthesis scripts
  • Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros
  • Extensive VHDL/Verilog 2001 test bench
  • Documentation
  • 30 days of technical support
  • 90 days of warranty against defects

Delivery Options

  • EDIF netlist for FPGA and low volume production
  • One-year maintenance
  • On-site support and training

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