I²S-SC - Philips® Inter-IC Sound Bus Single Channel Controller

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The I²S-SC core is a configurable single channel Inter-IC Sound (I²S) bus interface controller that combines functions of both transmitter and receiver. In order to facilitate the use of the I²S-SC core in various standard bus based microprocessor systems, different bus wrappers are provided, such as AMBA AHB and APB, and CoreConnect™ PLB.

The I²S-SC core supports a wide range of transmission parameters that are configurable through SFR registers, thus extending the functionality of the core beyond the I²S standard.

  • Highlights & Benefits
  • Configurability
  • Applications
  • Deliverables

Highlights

  • Meets Philips® Inter-IC Sound Bus specification
  • I²S Philips, left/right justified, DSP channel and Time Division Multiplexing modes supported
  • Native OCP socket with wrappers for AMBA® AHB, AMBA® APB or PLB system bus interfaces
  • Support for one stereo channel with up to 16 optional channels (with TDM support)
  • Two clock domains - host side and system clock
  • One set of SCK (SCLK) and WS (LRCLK) strobes
  • Separate, configurable FIFO buffer for transmit and receive channels
  • Interrupts driven by the I²S bus activity events
  • Handshake interface to external DMA modules

Benefits

  • Flexible system bus type selection
  • Simple development of I²S based digital audio interface with wide range of vendor specific transmission formats
  • Single solution for standard I²S interface as well as for multichannel TDM interface
  • Serial clock (SCK) polarity
  • Word select (WS) polarity
  • Frame synchronization / word select mode
  • Audio channel width
  • Data align within audio channel and host data bus
  • Data delay
  • Sample bit order
  • Audio/mono mode
  • Time Division Multiplexing (TDM) implementation
  • Size of external FIFO (default value is 16 words)
  • Width of data registers – maximum audio data width
  • Host-side interface type
  • Width of host data buses
  • Applications requiring multiple channel audio data transmission
  • Connecting Analog to Digital and Digital to Analog converters with very low jitter
  • Error correction for compact disc and digital recording
  • Digital signal processing and multimedia systems in general
  • Digital audio interface of embedded microcontroller systems

Deliverables

  • VDHL/Verilog source code
  • AMBA® APB wrapper
  • Synthesis support for Synopsys® and Cadence tools with a set of synthesis scripts 
  • Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros
  • Extensive VHDL/Verilog 2001 test bench
  • Documentation
  • 30 days of technical support 
  • 90 days of warranty against defects

Delivery Options

  • EDIF netlist for FPGA and low volume production
  • One-year maintenance
  • On-site support and training

Downloads

Product Versions

I²S-MC – the basic version of the I²S-SC IP core, which implements eight channels of Inter-IC Sound (I²S) serial buses and combines transmitter and receiver tasks.

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