Highlights

• Meets Philips® Inter-IC Sound Bus specification
• AMBA® APB bus slave interface
• I2S Philips, left/right justified and DSP modes supported
• 8 configurable stereo channels
• Two clock domains - host side and system clock
• Two sets of SCK (SCLK) and WS (LRCLK) strobes
• Two configurable FIFO buffers
• One configuration register block for all channels
• Interrupts driven by the I2S bus activity events
• Handshake interface to external DMA modules

Benefits

• Advanced configurability
• Support for multi-channel collection
• Synthesis parameters for adjusting the I2S IP core to the target application
• Configurable internal FIFO for data collection, which allows the system to process the audio stream in the interrupt triggered subroutine

• Depth of external FIFO (default value is 16 words)
• Width of data word in the FIFO
• Width of AMBA address bus

• Alignment of shorter audio data samples on the system bus
• Mode selection (Philips, Left/Right Justified, DSP)
• Software configurability of operation mode

• ASIC and SoC applications requiring multiple channel audio data transmission
• Connecting Analog to Digital and Digital to Analog converters with very low jitter
• Digital audio interface of embedded microcontroller systems

• Digital signal processing and multimedia systems in general
• Error correction for compact disc and digital recording

Deliverables

• Verilog source code
• AMBA® APB wrapper
• Synthesis support for Synopsys® and Cadence tools with a set of synthesis scripts 
• Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros
  
• Extensive Verilog test bench
• Collection of test cases
• Documentation
• 30 days of technical support 
• 90 days of warranty against defects

Delivery Options

• EDIF netlist for FPGA and low volume production
• One-year maintenance
• On-site support and training