NAND Flash PHY

SDLL-NANDFLASH-PHY - Synthesizable Digital Locked Loop PHY for the NAND Flash Memory Controller

The SDLL-NANDFLASH-PHY IP core allows to work with ONFi 1.x and 2.x compliant High-Speed NAND Flash memories.

In conjunction with the memory controller the SDLL-NANDFLASH-PHY forms a complete system and provides System-on-Chip developers with a comprehensive way to leverage emerging embedded application technologies and maximize their performance while minimizing time-consuming hardware and software development.

Highlights & Benefits
Target Technology
Applications
Deliverables

Highlights

By-pass mode for asynchronous operating mode
Compatible with ONFi 1.x and 2.x standards
Compatible with ToggleMode 1.0
No additional PLL required
Small area
Low power

Benefits

Source synchronous (High Speed DDR mode) and asynchronous interfaces support
Support for ONFi 1.x and 2.x standards speeds up time-to-market for products basing on NAND Flash technology

The SDLL-NANDFLASH-PHY is currently available on the LFoundry 150nm process with the possibility to port it to other technology nodes on request.

Mass Storage - USB flash drives, digital cameras, digital voice recorders, Solid State Drives (SSD)

Embedded Storage — cellular phones, network routers, point of sale systems

Deliverables

Verilog source code
Synthesis support for Synopsys® tools with a set of synthesis scripts
Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros
Basic HDL test bench
Stimulus files
Expected simulation results
Documentation
30 days of technical support
90 days of warranty against defects

Delivery Options

GDSII hard macro
Synopsys Design Compiler netlist

Downloads

Related Products

NANDFLASH-CTRL – the ONFi 2.2 compliant controller for high-capacity Multi-Level Cell (MLC), Single-Level Cell (SLC) and High-Speed NAND Flash memories.