Highlights

• Support for High Speed NAND Flash memories  (up to 200 MT/s)
• Support for Standard and Enhanced ClearNAND
• Support for Toggle Mode DDR NAND Flash devices from Toshiba and Samsung
• Compatible with ONFi 1.x and 2.2 standards and ONFi-compliant manufacturers (Micron)
• Internal OCP socket for straightforward implementation into custom system bus interfaces
• Available with AMBA AHB, PLB, Avalon and FlexBus system bus interfaces

Benefits

• Support for ONFi 1.x and 2.2 standards speeds time-to-market
• Ability to connect SLC and MLC memories simultaneously
• Source synchronous (High Speed DDR mode) and asynchronous interfaces support
• Seamless SoC integration with a built-in OCP socket
• The BCH ECC algorithm allows up to 64-bit error correction
• IP configuration script for cutting obsolete functional blocks

• Big or Little Endian Type
• Both synchronous (DDR mode) and asynchronous interfaces or only asynchronous interfaces
• Support for 512 B to 16 kB page size as defined in the ONFI spec
• Implementation of a DMA controller, Write/Erase Protection and hardware support for Bad Block Management

• 2-64 bit BCH Error Correction Code
• Timing parameters
• Number of address cycles
• ECC calculation
• Protected area size
• Implementation of interrupts

• USB flash drives
• Digital cameras
• Digital voice recorders

• Cellular phones
• Network routers
• Point of sale systems

Deliverables

• Verilog source code 
• Synthesis support for Synopsys® and Cadence® tools with a set of synthesis scripts 
• Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros 
• Extensive Verilog testbench 
• Documentation
• 30 days of technical support 
• 90 days of warranty against defects

Delivery Options

• EDIF netlist for FPGA and low volume production 
• One-year maintenance 
• On-site support and training