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USBHS-HUB - USB 2.0 High Speed Hub Controller

USBHS-HUB Block Diagram

The USBHS-HUB is a configurable USB 2.0 hub controller compliant with the USB Hi-Speed specification and the Link Power Management addendum featured in the SuperSpeed USB 3.0 hub controller.

The device provides various interface options,  from 8/16 bit UTMI+ through direct analog front  end (AFE) to a PHY-integrated USB interface.

The USBHS-HUB also features support for the  USB High Speed Inter Chip communication, with each port separately configurable to enable or disable this interface.

Apart from handling USB transactions, the group of main functional tasks performed by the USBHS-HUB includes connectivity behavior, connect/disconnect detection, power management, bus fault detection and recovery.

The USBHS-HUB contains the Transaction Translator module that translates Hi-Speed upstream port transactions to Low-/Full-Speed downstream ports transactions.

  • Highlights
  • Benefits
  • Configurability
  • Applications
  • Deliverables
  • Complies with the USB 2.0 High Speed specification and the Link Power Management addendum
  • Support for Hi-Speed, Full-Speed and Low-Speed devices
  • 3 interface options:
    - 8/16-bit UTMI+ with Hi-Speed serial mode support
    - Direct interface to analog front end (AFE)
    - USB interface (with integrated PHY)
  • Support for standard and hubspecific requests
  • Single or Multiple (optional) Transaction Translator for USB Low-/Full Speed transfers
  • Up to 15 downstream ports
  • Each port can be configured to support HSIC interface
  • Connect/disconnect detection of downstream ports
  • L0/L1/L2/L3 power operating modes
  • Technology independent, synthesizable design
  • Easily adoptable to user’s design thanks to 3 different interface scenarios
  • Link Power Management implementation for aggressive power savings and USB 3.0 HUB
  • A wide range of user configurable features allow customization and optimization for a specific design
  • Size of the On-Chip Hub Descriptor memory
  • Number of downstream ports
  • Number of transaction translator buffers
  • Type of PHY interface
  • HSIC option (per port)
  • SuperSpeed USB 3.0 Hub Controller
  • Personal computers
  • Docking stations
  • Set top boxes
  • Mobile phones

Deliverables

  • HDL source code
  • Synthesis support for Synopsys® tools with a set of synthesis scripts
  • Simulation support for Mentor Graphics® or Cadence® tools with a set of scripts and macros
  • Extensive HDL testbench
  • Documentation
  • 30 days of technical support 
  • 90 days of warranty against defects

Delivery Options

  • EDIF netlist for FPGA and low volume production
  • GDSII layout file for implementation with the USBHS-PHY
  • One-year maintenance
  • On-site support

Downloads

Product Versions

The USBHS-HUB can be ordered in the following configurations:

  • USBHS-HUB-E – the previous generation of the USBHS-HUB, now optimized for embedded use,
  • USBHS-HUB-D – the USBHS-HUB with the UTMI+ interface (digital IP only)
  • USBHS-HUB-DPHY – the USBHS-HUB with the Analaog Front End (AFE) interface (digital IP and digital PHY)
  • USBHS-HUB-PHY – The USBHS-HUB with the Evatronix USBHS-PHY - the complete hub solution
  • USBFS-HUB-D – a subset of the USBHS-HUB, supporting just the Full Speed path (digital IP only)
  • USBFS-HUB-PHY – a subset of the USBHS-HUB with the Evatronix USBHS-PHY, a complete solution for Full Speed path only

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