TVOUT-CTRL - Video Display Controller

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The TVOUT-CTRL is a synthesizable core which implements a video display controller compatible with the ITU-R BT.601/BT.656 recommendation (formerly CCIR-601 and CCIR-656). The Video DAC interface of the controller is compatible with Analog Devices’ ADV7174/79 video encoder chip  or a similar PAL or NTSC video encoder device.

The TVOUT-CTRL accepts three different input formats and produces 4:2:2 YCbCr pixel data. It generates all of the required control signals: horizontal synchronization (HSYNC), vertical synchronization (VSYNC) and video blanking (BLANK).

  • Highlights
  • Benefits
  • Configurability
  • Applications
  • Deliverables
  • Produces video data that meets the ITU-R BT.601/BT.656 recommendation (without SAV and EAV features)
  • AMBA® AHB system bus interface
  • PAL or NTSC video signal generation
  • Dedicated unidirectional DMA controller with burst transaction support
  • Accepts display data inputs in three formats - RGB 24 bits per pixel, RGB 15 bits per pixel and 4:2:2YCbCr
  • Internal, event stimulated, interrupt request generation with masking capability
  • Configurable internal FIFO
  • Integrated test mode – the core generates color bar without any AHB bus transactions
  • Integrated test mode – the core generates color bar without any AHB bus transactions
  • Power Save Mode
  • Seamless AMBA® AHB bus integration
  • Technology independent design
  • Designed for efficient implementation and straightforward testing in ASIC or FPGA SoC designs

The TVOUT-CTRL core has a set of synthesizable parameters that allow adjustment of the core for a particular application:

  • Depth of the FIFO memory
  • Active edge of the clock that synchronizes the reset signal

 

 

 

The TVOUT-CTRL is ideal for use in conjunction with a video data encoder such as the Analog Devices® ADV7174/79 or similar PAL or NTSC video encoder chip. Typical applications include:

  • Industrial television
  • Digital PAL or NTSC cameras
  • Portable video systems

Deliverables

  • RTL source code
  • Synthesis support for Synopsys® tools with a set of synthesis scripts 
  • Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros
  • Extensive Verilog 2001 test bench
  • Documentation
  • 30 days of technical support 
  • 90 days of warranty against defects

Delivery Options

  • EDIF netlist for FPGA and low volume production
  • One-year maintenance
  • On-site support and training

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