Design Services

Every piece of Evatronix IP is designed to meet the whole spectrum of applications it might be used in. When necessary, we can either provide configuration scripts or customize the IP in-house for best fit for your design.

Since the development of the first Evatronix IP core in 1997, we have been gaining extensive experience in designing IP cores with pin-to-pin or functional equivalency to the existing obsolete chips.

The Verification Specification describes the methods employed to verify the correctness of the design and provides an architectural overview of the verification environment. The Test Plan contains a list of elements crucial for functional verification – both the design’s key features as well as details of the related test cases.

At Evatronix, we are able to design a whole application that is based on our products and provide you with working netlists to meet your design requirements. Thanks to our cooperation with Xilinx, Altera, Actel and other FPGA providers, we will optimize the design for a specific family and device so that you get maximum performance at minimum gate count and cost.
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