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tech articlesAt Evatronix we track all the relevant industry news and specifications to bring the useful ones to our products, and eventually - to your designs. In many cases, we are the authors or co-authors for publications you read.

We share our knowledge for you to become a better designer. Read some tips, learn the tricks, know the traps - all this invaluable wisdom can be found in the articles below.

Some articles are publications prepared for various conferences - IP-SoC, CDN Live!, ChipEx, SSIPEX, and others.

Creation of such a comprehensive article data base would not be possible if it wasn't for help from co-authoring companies: Mohagi and Magillem.

  • How to Achieve The Highest Data Rate in NAND Flash Application
    The recent years brought significant changes and improvements to the NAND Flash technology, and this article will elaborate to how to take full advantage of the latest features of the controllers and standards while avoiding the traps of the technology. Various issues will be discussed, from I/O limitations to the increased ECC requirements.
  • Behavioral Modeling Facilitates Chip-Package Codesign
    Evatronix' mission was to develop a USB2 IP block. Compliance with USB2 specs requires good package design as well as good chip design. Managing the complexity of many tradeoffs is a tough EDA challenge. Once we had identified a viable pinout, signal integrity and power-integrity strategy, we found that it was straightforward to elaborate and optimize transistor-level layout and design of this chip.
  • The New Kid On The USBlock - Introducing SuperSpeed 3.0
    The USB 3.0 specification was approverd in 2008 adn the first certified products to take advantage of its SuperSpeed (5Gbit/s) were launched at January's Consumer Electronics Show in Las Vegas.
    This article provides a high-level overview of the USB 3.0's potential, its limitations and new features (including power management).
  • The “off-the-shelf” IPs for today’s SoCs
    Today SoC designs are highly complex with many functionalities. Do these functionalities need to be developed entirely in-house? Rather not! From this paper a reader will get advice on when they should choose third party IP vendor instead of developing standard component in-house.
  • A high-performance VLSI Architecture of 2D DWT Processor for JPEG2000 Encoder
    In this paper we propose a hardware architecture of the lifting-based, two-dimensional discrete wavelet transform. The proposed architecture implements both lossless (5/3) and lossy (9/7) multi-level DWT with an embedded, symmetric tile extension. This article discusses optimization methods, introduced to increase design throughput up to 800 MSamples/s and solutions that rationalize the circuit area. The results of synthesis for FPGA and ASIC technology are presented.
  • Hardware Solutions to the Challenges of Multimedia IP Functional Verification
    This paper discusses the functional verification of IP cores and problems which arise during their implemenation in today’s advanced applications. First, the usual approach to functional verification is presented together with its common difficulties. The next part features an example of hardware verification environment which was used for verification of the Evatronix JPEG 2000 encoder multimedia IP core in order to illustrate this paper’s thesis.
  • Straightforward IP Integration with IP-XACT RTL-TLM Switching
    This paper gives the results of experimentations done for the packaging of a USB OTG controller respecting the IP-XACT schema provided by the SPIRIT Consortium. It presents the advantages and the technical facts for an IP provider to deliver standardized files package, bringing great advantages for documentation, integration and verification purposes.
  • High-performance Architecture of the JPEG 2000 Encoder
    The article presents a hardware architecture of JPEG2000 encoder core, oriented for HD video broadcast and surveillance applications. Thanks to developed efficient 2-D DWT engine that is capable of computing four coefficients per clock cycle, and adopted two EBCOT TIER-1 modules, with smart switching of the channels, the maximum compression speed of 180 Msamples/s at 100 MHz is achieved.
  • A high-performance VLSI Architecture of 2D DWT Processor for the JPEG 2000 Encoder
    In this paper we present a hardware architecture of the lifting-based, two-dimensional discrete wavelet transform. The proposed architecture implements both lossless (5/3) and lossy (9/7), multi-level DWT with an embedded, symmetric extension at tile boundaries. This article discusses optimization methods introduced to increase design throughput up to 800 MSamples/s and solutions that rationalize the circuit area. The results of synthesis for FPGA and ASIC technology are presented.
  • Verification of the JPEG2000 Encoder Based on Rate and Distortion Curve Analysis
    The article presents a methodology of JPEG2000 compression system verification based on a rate and distortion curve analysis. In the paper issues of subjective and objective image quality metrics are discussed, with special focus on “fullreference” methods. Authors propose division of the test images, into several groups, of similar spatial frequency content and the same resolution.
    Performed experiments revealed normal distribution of PSNR and deltaPSNR random variables, defined for reconstructed images. The elaborated methodology takes advantage of the normal distribution’s three-sigma rule to smart classification of failed tests.

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