Evatronix Standardizes on TransEDA for IP Quality Excellence

Los Gatos, Calif. (USA); Bielsko - Biala, Poland - February 20, 2002 - TransEDA® PLC, the leader in ready-to-use verification solutions and Evatronix SA, IP cores and design services provider, today announced that Evatronix S.A. has standardized on TransEDA's Verification Navigator integrated design verification environment as a vital part of its intellectual property (IP) quality assurance policy. Evatronix is a leading provider of IP and design services.

"Leading IP consumers trust Evatronix to provide reliable and verified design cores, so quality assurance is our number one priority," said Wojciech Sakowski, vice president of Evatronix. "Our decision to invest in TransEDA's tools is already proving extremely valuable. With our previous methodology, we performed extensive simulations and rigorous prototype testing, but we weren't completely confident that the results were bug-free. TransEDA has greatly improved our confidence using much less time and effort."

Tom Borgstrom, vice president of marketing at TransEDA said, "The demand for high quality IP from suppliers such as Evatronix continues to rise. Additionally, the larger semiconductor and system houses are making proven IP qualification a mandatory requirement when selecting third-party IP. TransEDA's verification tools provide companies like Evatronix with significant advantages in reaching quality goals. By setting coverage standards and improving code quality, we can help Evatronix and other IP vendors deliver first-rate IP that their customers can trust."

Verification Speeds IP Core Development and Improves Quality

Evatronix has defined and implemented a new verification plan as part of its IP design and qualification process. It relies on the TransEDA Verification Navigator product suite for coverage analysis, hardware description language (HDL) and design rule checking, and test suite analysis. TransEDA's VN-Cover™ coverage analysis solution helps Evatronix measure the effectiveness of the test suite developed for a particular core. Its ease-of-use enables the creation and enforcement of stringent corporate goals for coverage of all possible conditions by the test suite.

"We used VN-Cover on our CZ80sio project to improve the test suite and meet our 100 percent statement, 100 percent branch, and 90 percent condition coverage standards. VN-Cover immediately proved its worth by revealing a new bug," said Miroslaw Bandzerewicz, quality assurance manager at Evatronix. "We used VN-Check™ configurable HDL checker for the static verification of HDL code quality and design rule compliance. In addition to verification, it also partially automated rating cores against industry standard reusability rules, helping us to better comply with these important objectives."

Evatronix has also adopted the TransEDA VN-Optimize™ test suite analysis tool, which reduces verification time by optimizing the test suite to achieve coverage goals with the fewest number of tests. "We used to perform full core verification after every code change, but this took much too long," said Adam Bitniok, project manager of a math coprocessor design. "VN?Optimize helps us do just the right amount of testing. With our C80187 coprocessor project, we went from 3,368 test sets to 212, with just a four percent drop in coverage."