Evatronix to present on IP Verification during the ChipEx 2010 Conference in Israel on May 4th.

Bielsko-Biala/Poland, April 26^th, 2010 - The silicon intellectual property (IP) provider, Evatronix SA, today announced it will host a technical presentation during the ChipEx 2010 Conference held in Israel on May 4th. ChipEx Conference is the leading international event of the Israeli semiconductor industry, with multiple plenary sessions and eight technology tracks. The conference includes a GSA Executive Forum event, dedicated to celebration of the 30th anniversary of the EDA industry.

In the lecture Ireneusz Sobanski, Senior Verification Engineer at Evatronix, will discuss the importance of software based IP verification and the influence it has on speeding up the development of System-on-Chip hardware and firmware. The presentation concentrates on elaborating the methodology where functional verification environment could be used as the starting point for the embedded software development and an accelerator to the overall design process.

"Simultaneous creation of a SystemC TLM model alongside the RTL source code not only reduces the verification time, but also gives the SoC team a unique opportunity to develop hardware and software together," said Michal Jedrak, Technical Marketing Manager at Evatronix. “Also, basing the functional tests on software routines allows the creation of a full Hardware Abstraction Layer (HAL) already during the verification phase. Therefore the firmware functions can be based on actual HAL functions, thus reducing the firmware development time and increasing the software reliability.”

The ChipEx 2010 Conference will be a great opportunity for SoC designers to learn not only about the IP verification issues, but also find out more about the Superspeed USB 3.0 controller IP, the fastest 8051 microcontroller, ONFi 2.2 compatible NAND Flash memory controllers and SDIO 3.0 / eMMC 4.4 host controllers, all available from Evatronix.