Evatronix Enhances its USB Portfolio with High Speed Inter-Chip (HSIC) Compatible PHY IP

Direct chip-to-chip interconnect allows significant power and silicon area savings while retaining all performance features of the USB 2.0 standard.

Bielsko-Biala/Poland, February 15th, 2011 - Evatronix SA, the leading provider of USB-IF certified solutions for SuperSpeed USB 3.0 and USB 2.0 IP, have announced today the introduction of a High Speed Inter-Chip (HSIC) compatible PHY IP for significant power and area savings in USB 2.0 chip-to-chip connections. Implementation of the HSIC technology enables setting up a direct connection on a PCB board between a USB Host chip and other on-board USB devices. The HSIC standard features much less power consumption thanks to elimination of requirements to support long external USB cables while remaining USB protocol compliant and thus USB software compatible. The possibility for straightforward use of all the available USB software gives HSIC an advantage over other inter-chip connection standards, like I2C.

"The introduction of the USBHSIC-PHY is the next step in the Evatronix strategy of delivering complete USB solutions," said Wojciech Sakowski, Evatronix CEO. "With a silicon-proven suite of controllers, software stacks and OS drivers already in our portfolio, we are now complementing our offering with the USBHSIC-PHY to enable straightforward implementation of the USB 2.0 chip-to-chip connectivity with all components from a single IP vendor."

Through the implementation of a 240MHz DDR interface the HSIC standard provides full support for the 480Mbps data transfer of the USB protocol. By elimination of 3.3 and 5V signaling the HSIC interface enables significant silicon area and power savings in comparison to standard cable USB 2.0 PHYs.

EVATRONIX USBHSIC-PHY AVAILABILITY

The Evatronix USBHSIC-PHY logic macro is available now on the LFoundry 150nm process with the possibility to port it to any technology node from 65 to 180nm.